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SPACE POWERLINK DEVELOPMENT

ESA Open Invitation To Tender AO8435
Open Date: 16/09/2015
Closing Date: 28/10/2015

Status: ISSUED
Reference Nr.: 15.1ED.05
Prog. Ref.: EOEP-4 EO Prep. Acti;TRP
Budget Ref.: E/0092-E4 - EOEP-4 EO Prep. Acti;E/0901-01 - TRP
Special Prov.: BE+DK+FR+DE+IT+NL+ES+SE+CH+GB+IE+AT+NO+FI+PT+GR+LU+CZ+RO+PL
Tender Type: C
Price Range: > 500 KEURO
Establishment: ESTEC
Directorate: Directorate of Technical & Quality Manag
Department: Electrical Engineering Department
Division: Data Systems Division
Contract Officer: Fabrizi, Lavinia
Last Update Date: 17/09/2015
Update Reason: Loaded a new Clarification(English version)

Current spacecraft architectures include segregated power, data communication, and monitoring discrete lines. This leads to a bulkyand heavy harness (e.g. up to 15% of the dry mass). The Remote Terminal Unit (RTU) traditionally handles the connections to sensorsand actuators by a centralized star topology harness. The previous TRP activity T701-001ED ‘PowerLink: 2-wire Power and Data’ has been completed in January 2015 and demonstrated the feasibility of a system for controlling low power actuators and sensors via a very efficient, low mass, robust, and scalable network, which transports both the power and the data exchanges over only 2-wire to the sensor/actuator. The demonstrator included small boards linked by a simple 2-wire bus performing the PowerLink (PwL) controller and a set of PwL terminals interfacing a set of representative sensors and actuators. The demonstrator passed all required electrical, EMC and TM/TC tests. The study also showed that the PwL system approach could have resulted in a mass saving of 19 kg in the Bepi Colombo case (50% mass saving). The present proposed activity builds on the functions and the performances of the previous TRP activity. In particular, standardisation of on-board spacecraft architectures shall be achieved by developing a PwL Controller/Terminal ASIC(Application Specific Integrated Circuit) that can be configured either as controller (master) or as Terminal (slave) in any satellite. The ASIC will include a generic part that ensures the interface compatibility between any Controller/Terminal connected to the PwL bus, and a specific part (e.g. ADC) which is application dependent and does not affect that compatibility. The generic part willbe designed in the form of (mix-Analog PwL Bus) IP Core and its ownership shall be delivered to the Agency for further dissemination to the Space Industry in order to facilitate the quick adoption and scaleability by all industrial teams working on equipment using the PwL interface. The specific part will also be designed, since it is part of the PwL Controller/Terminal ASIC. The proposed activity (Phase-1) includes: - the specification and design of the full PwL Controller/Terminal ASIC, including the (mix-Analog PowerLink Bus) IP Core. - the selection of technology to manufacture the PowerLink Controller/Terminal ASIC, - the delivery of a silicon proven IP Core, to be own by the Agency - the preparation of a Baseline PwL technology specification for standardization - the design of boards for characterisation and radiation testing. Subject to the availability at the end of Phase 1 of additional budget, this activity will be continued to Phase 2 to reach TRL 5 and to complete the work of Phase-1 with the following tasks: - manufacturing ofthe PwL Controller/Terminal ASIC - manufacturing of the boards for the PwL characterisation and radiation testing - characterisation and radiation testing of the PwL Controller/Terminal ASIC Phase 2 is expected to be of similar budget and duration than phase 1. Being of strong generic interest, the phase 1 of this activity is supported by Science Programme and co-funded by TRP with Earth Observation Programme. TRP, Earth Observation and Science Programme also intend to co-fund the phase 2 of this activity, pending satisfactory completion of phase 1.

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